• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method of transmitting data between a transmitting electronic device and a receiving electronic device connected to one another by a data link, comprising the steps of: - sending the data in the form of at least three identical frames sent successively and each associated with a validity information calculated on the frame concerned, - check the validity of the received frames as and when they are received by the receiving electronic device and make available for processing the first valid frame and ignore the others.
    公开号:FR3024932A1
    申请号:FR1457839
    申请日:2014-08-14
    公开日:2016-02-19
    发明作者:Laurent Morel-Fourrier；Mathieu Conq；Nicolas Geneste
    申请人:Sagem Defense Securite SA；
    IPC主号:
    专利说明:

    [0001] The invention relates to securing the transmission of data between electronic devices. These electronic devices are for example computers used for piloting an aircraft. In an aircraft, the engine (s) are controlled by an engine control unit (ECU) comprising a plurality of electronic data processing devices such as computers connected to each other by serial links. which frames of data are exchanged. These series links are subject to disturbances, resulting for example from electric and / or electromagnetic fields and lightning strikes, which can alter the data transmitted on the links. Despite this, it is necessary that the engine control is not altered in these circumstances. An object of the invention is to improve the reliability of data transmission. For this purpose, according to the invention, there is provided a method for transmitting data between a transmitting electronic device and a receiving electronic device connected to one another by a data link, comprising the steps of: - sending the data data in the form of at least three identical frames sent successively and each associated with a validity information item calculated on the frame concerned, - checking the validity of the received frames as and when they are received by the receiving electronic device, making available to process the first valid frame and ignore the others.
    [0002] 3024932 2 The time multiplication of the frames limits the risk that a disturbance alters the transmitted data. In addition, the presence of the validity information facilitates the detection of corrupted frames by the receiving device and speeds up the processing of the data. Advantageously, the method comprises the step, when none of the received frames is valid, to reconstitute a frame by majority vote from the three received frames. The comparison of the data of the received frames makes it possible to simply reconstitute a frame, for example by a majority voting algorithm, thus eliminating errors that would result from a disturbance.
    [0003] Advantageously then, the method comprises the steps of calculating validity information on the reconstituted frame, and making available for processing the reconstituted frame if it is valid. The robustness of the transmission is further improved. Preferably, the frame reconstruction is performed as and when the data of the third frame is received. The need for memory is thus limited while the speed of treatment is favored. Preferably then, the receiving electronic device having at least a first buffer area and at least a second buffer area: the first received frame and its validity information are stored in the first buffer area; if the first received frame is not valid, the second received frame and its validity information are recorded in the second buffer area; If the second received frame is not valid, the third received frame and its validity information are recorded in the first buffer zone; The reconstituted frame and its validity information are recorded in the second buffer zone. This limits the buffer requirements. Advantageously, the data link being capable of undergoing a disturbance of predetermined theoretical maximum duration, the frames are spaced apart by an interleaving time greater than the predetermined theoretical maximum duration. Interleave time is counted from the start of the transmission of a frame at the beginning of the transmission of the next frame. Thus, the same disturbance can not alter the same bit of two successive frames. Advantageously, the data link being capable of undergoing two consecutive disturbances 20 spaced apart by a predetermined minimum theoretical duration, each frame has a duration less than the predetermined theoretical minimum duration. The risk of a frame being altered by two consecutive disturbances is thus limited.
    [0004] The invention also relates to a data processing assembly comprising at least one transmitting electronic device and one receiving electronic device connected to one another by a data link, the electronic devices being arranged to implement the process of the invention. Other characteristics and advantages of the invention will emerge on reading the following description of a particular and non-limiting embodiment of the invention.
    [0005] FIG. 1 is a schematic view of a device embodying the invention; FIG. 2 is a block diagram illustrating the various steps of the process of the invention; FIG. 'invention. With reference to the figures, the method according to the invention is implemented in an apparatus comprising two electronic devices 1A, 1B each comprising a processing circuit 2A, 25, such as a processor associated with a random access memory and a memory massive. The RAM comprises two buffer areas dedicated to temporary storage of the transmitted data (the buffer areas are noted in the buffer memory 1 and buffer 2 for convenience and without reference to the figures). Each processing circuit 2A, 2B is connected to a communication interface 3A, 33. The communication interfaces 3A, 3B are connected to each other through filters 4A, 4B via a serial link 5. The devices 1A, 1B can be alternately transmitter and receiver. These different components have a known structure in themselves and will not be described in more detail. In operation, data frames are transmitted between the electronic devices 1A, 1B to be processed by the processing circuits 2A, 23. The apparatus is arranged to implement a transmission method which is based on: - the side from the transmitter, a time triplication such that each data frame is sent three times (frame 1, 2, 3) with a validity data item associated with each frame; on the receiver side, a frame correction based on the validity information and a bit-by-bit majority voting algorithm.
    [0006] The devices 1A, 1B are more precisely arranged to implement the data transmission method comprising the steps of: for a data frame to be transmitted, preparing at least two replicated frames to obtain a set of three frames to be transmitted. (this is the triplication operation); calculate on each frame validity information and associate it with each frame; Transmitting the frames successively over time with their validity information; checking the validity of the first received frame with its validity information and, if successful, processing the first frame and neglecting the other frames of the same set of frames; if the first received data frame is not valid, wait for the next frame and check the validity of the second received frame with its validity information and, if successful, treat the second frame and neglect the other frames of the same frame. set of frames; if the second received frame is not valid, wait for the next frame and compare, on the fly and bit by bit, the third frame received with the first received frame and the second received frame to reconstruct a frame by means of a majority voting algorithm and calculating validity information of the reconstituted frame; Verifying the validity of the third frame and if the third frame received is valid, processing the third frame received; if the third received frame is not valid, check the validity of the reconstructed frame 35 and treat the reconstituted frame if it is valid and neglect it if the reconstituted frame is not valid. The validity information is here the result of a Cyclic Redundancy Check (CRC), for example a checksum (or checksum), which makes it possible to check the data integrity of the frame. This type of control is known in itself. On the receiver side, frames 1 and 2 are stored in a buffer memory. The frame 3 is used to carry out, if necessary, an error correction on the fly. More precisely, the frame 3 is compared in real time, bit by bit, with the frames 1 and 2 previously received and stored: this makes it possible to reconstitute in real time a corrected frame which is stored in the buffer memory. As each frame is associated with validity information, the processing circuit of the receiving device can check the validity of each received frame. Each frame is therefore checked against its own validity information. The first frame that is received, and whose validity is confirmed by the validity information, is used for processing.
    [0007] Therefore, during reception: - the first received frame whose validity is confirmed is made available for processing; the following frames of the frame set are ignored. If the frame 1 (first received frame) is validated (step 10), the frame 1 is made accessible for the processing to be performed and the frames 2 (second received frame) and 3 (third received frame) are ignored.
    [0008] If the frame 1 is not valid while the frame 2 is valid (step 20), the frame 2 is made accessible and the frame 3 is ignored. If the frames 1 and 2 are not valid, the receiving device performs error detection on the frame 3. Each word of the frame 3 is compared (bit by bit) with the received words of the frames 1 and 2. The bits majority are memorized and form a reconstituted frame.
    [0009] If frame 3 is enabled (step 30), then frame 3 is made available for processing and frames 1 and 2 are ignored. If the frame 3 is not correct, the receiver checks the validity information of the reconstituted frame 3. If the validity information is correct (step 40), then the reconstituted frame is made available. If the validity information is not correct, then the data transmission is considered to have failed (step 50). An example of received frames and reconstituted frame is shown in the table below. While the received data frames 1, 2 and 3 should be identical (since they are identical prior to transmission), it is apparent that they are different due to errors introduced during transmission. CRC1, CRC2, CRC3 and CRC4 are the validity information respectively of the frames 1, 2, 3, and the reconstituted frame.
    [0010] 30 Field 1 Field 2 Trame3 reconstructed frame 11011000 10010000 10011000 10011000 00110010 00110010 00110010 00110010 11110111 11110111 11110111 11110111 5 3024932 8 11000001 11000101 11001001 11000001 10011000 10011000 10011000 10011000 11101111 11111111 11111111 11111111 00110010 00110010 00110010 00110010 00000000 10011000 10011000 10011000 00110010 00110010 00110010 00110010 10011000 10011000 10011000 10011000 11011000 10010000 10011010 10011000 00110010 00110010 00110010 00110010 10011000 10011000 10011000 10011000 CRC1 CRC2 CRC3 CR04 Table 1 The different cases corresponding to the reception of the three frames are listed in Table 2 below. In this table, "OK" means that the frame is valid, "KO" means that the frame is not valid, "x" means that the frame is ignored. Frame Framing Frame Algorithm Algorithm 1 2 3 after correction OK X x X Store frame 1 in buffer 1. If CR01 is OK, then wait for a time longer than idle time (32 bits, "idle time") after end of frame 1 (frames 2 and 3 are ignored). Indicate that the data is available in the buffer memory 1. Store the frame 1 in the buffer memory 1. If CR01 is KO, then store the frame 2 in the buffer memory 2 and if OK K x X CR02 is OK, then wait for one longer than the idle time after the end of the frame 2 (the frame 3 is ignored). Indicate that the data in buffer 2 is available. KO KO OK X Store the frame 1 in the buffer memory 1. If CR01 is KO, then store the frame 2 in the buffer memory 2 and if CR02 is KO, then store the frame 3 in the buffer memory 1 and make a correction to 2. If CRC3 is OK, wait longer than the idle time after the end of frame 3. Indicate that the data in buffer 1 is available. KO KO KO OK Store the frame 1 in the buffer memory 1. If CR01 is KO, then store the frame 2 in the buffer memory 2 and if CR02 is KO, then store the frame 3 in the buffer memory 1 and make a correction to 2. If CR03 is KO and CR04 is OK, wait longer than the idle time after the end of frame 3. Indicate that the data in buffer 2 is available. KO KO KO KO Storage of the frame 1 in the buffer memory 1. If CR01 is KO, then store the frame 2 in the buffer memory 2 and if CR02 is KO, then store the frame 3 in the buffer memory 1 and perform a correction on the fly in the buffer 2. If CRC3 and CRC 4 are KO, wait for a time longer than the idle time after the end of the frame 3.
    [0011] 3024932 10 Indicate that the data is corrupted. Table 2 When all the frames have been received, there is only one case in which the data made available for processing are erroneous: the three frames have been corrupted and, in the bit-by-bit comparison, two of the frames have been corrupted. Frames share corrupted bits in the same way. Table 3 lists various possible cases when at least one transmitted frame has not been received. When one or more frames are missing, the field correction is not possible and the first correct frame received is used. Frame 1 Frame 2 Frame 3 Status Algorithm after correction Missing OK XN / A Store frame 2 in buffer 1. If CRC2 is OK, wait longer than the idle time after the end of frame 2 and ignore the frame 3. Indicate that the data in buffer 1 is available. Missing KO OK N / A Store frame 2 in buffer 1. If CRC2 is KO, store frame 3 in buffer 2. If CRC3 is OK, wait longer than idle time after end of frame 3. Indicate that the data in buffer 2 is available.
    [0012] 3024932 11 Missing KO KO N / A Store frame 2 in buffer 1. If CR02 is KO, store frame 3 in buffer 2. If CR03 is KO, wait longer than the idle time after the end of frame 3. Indicate that the data is corrupted. Missing KO Missing N / A Store frame 2 in buffer 1. If CR02 is KO, wait for more than the idle time after the end of frame 2. Indicate that the data is corrupted. MissingMaintain OK N / A Store Frame 3 in Buffer 1. If CR03 is OK, wait longer than idle time after end of frame 3. Indicate that data is corrupted. Missing KO N / A Store Frame 3 in Buffer 1. If CR03 is KO, wait longer than idle time after end of frame 3. Indicate that the data is corrupted. KO Missing OK N / A Store frame 1 in buffer 1. If CR01 is KO, store frame 3 in buffer 2. If CR03 is OK, wait longer than the idle time after the end of the frame 3. Indicate that the data of the buffer memory 3024932 12 are available. KO Missing KO N / A Store frame 1 in the buffer memory 1. If CRC1 is KO, store frame 3 in buffer 2. If CR03 is KO, wait longer than the idle time after the end of the frame 3. Indicate that the data is corrupted. KO MissingMore N / A Store Frame 1 in Buffer 1. If CRC1 is KO, wait longer than the idle time after the end of Frame 1. Indicate that the data is corrupted. KO KO Missing N / A Store frame 1 in buffer 1. If CRC1 is KO, store frame 2 in buffer 2. If CRC2 is KO, wait for a longer time than the idle time after the end of the frame 2. Indicate that the data is corrupted. Table 3 The mechanism of the invention combines a correction (triplication) mechanism with a validity check mechanism to have good robustness. Thus, most failures in transmission can be detected and corrected. In extreme cases where the correction is not possible, the failure is detected and the transmission is considered to have failed.
    [0013] The implementation of the invention does not involve any additional cost and requires only relatively low computing resources. The invention is usable for any data transmission between electronic data processing devices.
    权利要求:
    Claims (8)
    [0001]
    REVENDICATIONS1. A method of transmitting data between a transmitting electronic device and a receiving electronic device connected to one another by a data link, comprising the steps of: - sending the data in the form of at least three identical frames sent successively and each associated with a validity information calculated on the frame concerned, - check the validity of the received frames as and when they are received by the receiving electronic device and make available for processing the first valid frame and ignore the others.
    [0002]
    2. Method according to claim 1, comprising the step, when none of the received frames is valid, to reconstitute a frame by majority vote from the three frames received.
    [0003]
    The method of claim 2, comprising the steps of calculating validity information on the reconstructed frame, and making the reconstructed frame available for processing.
    [0004]
    The method of claim 2 or claim 3, wherein the frame reconstruction is performed as the data of the third frame is received.
    [0005]
    The method of claim 4, wherein the receiving electronic device includes at least a first buffer area and at least a second buffer area, wherein: the first received frame and its validity information are recorded in the first buffer area. buffer memory; if the first received frame is not valid, the second received frame and its validity information are recorded in the second buffer area; if the second received frame is not valid, the received third frame and its validity information are recorded in the first buffer area; the reconstituted frame and its validity information are recorded in the second buffer zone. 10
    [0006]
    6. Method according to claim 1, the data link being capable of undergoing a disturbance of predetermined maximum theoretical duration, in which the frames are spaced apart by an intermediate duration greater than the predetermined theoretical maximum duration. 15
    [0007]
    7. The method of claim 1, the data link being capable of undergoing two consecutive disturbances spaced by a predetermined minimum theoretical duration, in which each frame has a duration less than the predetermined theoretical minimum duration. 20
    [0008]
    8. A data processing assembly comprising at least one transmitting electronic device and a receiving electronic device connected to one another by a data link, the electronic devices being arranged to implement the method according to claims 1 to 7.
    类似技术:
    公开号 | 公开日 | 专利标题
    FR3024932A1|2016-02-19|METHOD FOR TRANSMITTING DATA WITH IMPROVED ROBUSTNESS AND SET OF DEVICES FOR IMPLEMENTING IT
    CN103106068A|2013-05-15|Internet of things big data fast calibration method
    CN102136887A|2011-07-27|Cyclic redundancy check method and device for transmission blocks
    EP2209009B1|2013-08-14|Aircraft control system with voting algorithm.
    CN107688503A|2018-02-13|A kind of message treatment method based on ActiveMQ data/address bus, device and electronic equipment
    US9312991B2|2016-04-12|Packet loss recovery on a wireless link in a transmission layer protocol session
    FR3014273A1|2015-06-05|SYSTEM FOR TRANSMITTING AVIONIC APPLICATIVE DATA
    WO2017068441A1|2017-04-27|Bandwidth throttling
    FR3014622A1|2015-06-12|ARCHITECTURE FOR CRITICAL DATA TRANSMISSION IN AVIONICS SYSTEMS
    EP2533458B1|2018-05-23|Method of generating a secret key for a wireless communication system
    JP4839364B2|2011-12-21|Combined command and data code
    FR3076639A1|2019-07-12|METHOD AND SYSTEM FOR SECURING DATA ISSUED BY AN OBJECT CONNECTED TO ATTACKS AFFECTING A CONTROL CIRCUIT OF SAID OBJECT
    FR3038752A1|2017-01-13|
    US6915471B2|2005-07-05|Encoder and method for encoding data
    US20160365948A1|2016-12-15|Method and a system for packet reconstruction
    FR2922699A1|2009-04-24|ITERATIVE DECODING IN A MESH NETWORK, CORRESPONDING METHOD AND SYSTEM
    WO2015092585A1|2015-06-25|Method and apparatus for cipher fault detection
    KR102119764B1|2020-06-05|Appartus and method for transmiting/receiving message packet in vehicle
    FR2992503A1|2013-12-27|DEVICE FOR CORRECTING AN ERROR OF AT LEAST N BITS IN A CODEWORD WHICH HAMMING MINIMUM DISTANCE IS LESS THAN OR EQUAL TO 2N
    EP2784680B1|2020-06-03|Method for running interlaced secured software and non-secured software
    EP3893117A1|2021-10-13|Circuit for checking the contents of records
    EP3552346A1|2019-10-16|Method of sending a message, method of reception, sending device, reception device and communication system associated therewith
    US20100269007A1|2010-10-21|Digitized radar information redundancy method and system
    WO2010049988A1|2010-05-06|Decoding device, reception device, communication system, decoding method, and reception method
    WO2006087497A2|2006-08-24|Frame-synchronisation method and device
    同族专利:
    公开号 | 公开日
    US10477539B2|2019-11-12|
    FR3024932B1|2017-12-01|
    CN106068500B|2017-12-05|
    US20170070989A1|2017-03-09|
    CN106068500A|2016-11-02|
    WO2015124538A1|2015-08-27|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5241548A|1991-05-23|1993-08-31|Motorola, Inc.|Method for error correction of a transmitted data word|
    EP0797326A2|1996-02-23|1997-09-24|Texas Instruments Deutschland Gmbh|Method of generating a corrected response signal from a corrupted digital response signal|
    US20020095635A1|2001-01-17|2002-07-18|Stefan Wager|Error correction using packet combining during soft handover|
    EP2453604A2|2010-11-12|2012-05-16|Honeywell International, Inc.|Systems and methods of providing error tolerant robust simplex wireless data for systems employing time correlated data transfer|
    US5455830A|1992-02-20|1995-10-03|Gregg; Thomas A.|Error detection and recovery in parallel/serial buses|
    US5673291A|1994-09-14|1997-09-30|Ericsson Inc.|Simultaneous demodulation and decoding of a digitally modulated radio signal using known symbols|
    FI106493B|1999-02-09|2001-02-15|Nokia Mobile Phones Ltd|A method and system for reliably transmitting packet data|
    EP1170870A4|2000-02-15|2006-08-02|Jfe Steel Corp|Turbo decoder|
    US6877043B2|2000-04-07|2005-04-05|Broadcom Corporation|Method for distributing sets of collision resolution parameters in a frame-based communications network|
    US6697441B1|2000-06-06|2004-02-24|Ericsson Inc.|Baseband processors and methods and systems for decoding a received signal having a transmitter or channel induced coupling between bits|
    US7352770B1|2000-08-04|2008-04-01|Intellon Corporation|Media access control protocol with priority and contention-free intervals|
    US7061866B2|2002-01-10|2006-06-13|Intel Corporation|Metered packet flow for packet switched networks|
    KR100584170B1|2002-07-11|2006-06-02|재단법인서울대학교산학협력재단|Turbo Coded Hybrid Automatic Repeat Request System And Error Detection Method|
    JP4110964B2|2002-12-25|2008-07-02|日本電気株式会社|Transmission system and data transfer method|
    US7539489B1|2003-04-04|2009-05-26|Veriwave, Incorporated|Location-based testing for wireless data communication networks|
    KR100638017B1|2003-05-30|2006-10-23|엘지전자 주식회사|Network device|
    JP4440037B2|2004-08-11|2010-03-24|株式会社東芝|Communication apparatus and communication method|
    US8031583B2|2005-03-30|2011-10-04|Motorola Mobility, Inc.|Method and apparatus for reducing round trip latency and overhead within a communication system|
    US7889654B2|2005-03-30|2011-02-15|At&T Intellectual Property Ii, L.P.|Loss tolerant transmission control protocol|
    US8331386B2|2007-02-07|2012-12-11|Agere Systems Llc|CRC checking and MAC-HS processing in an HSDPA-compatible receiver in a 3G wireless network|
    US7379450B2|2006-03-10|2008-05-27|International Business Machines Corporation|System and method for peer-to-peer multi-party voice-over-IP services|
    US8423855B2|2007-03-06|2013-04-16|Thomson Licensing|Adaptive and scalable packer error correction apparatus and method|
    KR101378257B1|2007-06-15|2014-03-25|삼성전자주식회사|Method for construction virtual backbone in wireless sensor networks|
    US8422411B2|2007-10-07|2013-04-16|Motorola Mobility Llc|Flexible frame structure in wireless communication system|
    WO2009141860A1|2008-05-19|2009-11-26|富士通株式会社|Verification device, verification method, and verification program|
    US8238247B2|2009-03-25|2012-08-07|Wi-Lan, Inc.|System and method for proactive repeat transmission of data over an unreliable transmission medium|
    WO2011034350A2|2009-09-21|2011-03-24|Lg Electronics Inc.|Method and apparatus for transmitting and receiving signal in relay station|
    US9094419B2|2009-11-10|2015-07-28|Netgen Communications, Inc.|Real-time facsimile transmission over a packet network|
    CN105591991A|2009-12-15|2016-05-18|意法半导体研发有限公司|Data communication device, data communication system and data communication method|
    CN101826038B|2010-04-28|2012-02-08|复旦大学|Circuit and method for resisting SEU of SRAM FPGA device|
    US8588347B1|2010-06-23|2013-11-19|Marvell International Ltd.|Systems and methods for performing efficient blind decoding at a wireless receiver|
    US8566669B2|2010-07-07|2013-10-22|Ocz Technology Group Inc.|Memory system and method for generating and transferring parity information|
    US8774043B2|2011-06-08|2014-07-08|Citrix Systems, Inc.|Methods and apparatus for using a layered gear to analyze and manage real-time network quality of service transmission for mobile devices on public networks|
    US9374194B2|2013-12-31|2016-06-21|General Electric Company|Transmission system error detection and correction system and method|
    US9178757B2|2013-12-31|2015-11-03|General Electric Company|Serial link fault detection system and method|
    FR3024932B1|2014-08-14|2017-12-01|Sagem Defense Securite|METHOD FOR TRANSMITTING DATA WITH IMPROVED ROBUSTNESS AND SET OF DEVICES FOR IMPLEMENTING IT|FR3024932B1|2014-08-14|2017-12-01|Sagem Defense Securite|METHOD FOR TRANSMITTING DATA WITH IMPROVED ROBUSTNESS AND SET OF DEVICES FOR IMPLEMENTING IT|
    WO2018041878A1|2016-09-02|2018-03-08|Abb Schweiz Ag|Improved voting for PROFIBUS line redundancy|
    JP6717214B2|2017-01-18|2020-07-01|株式会社オートネットワーク技術研究所|Communication device, communication system, and computer program|
    FR3071118B1|2017-09-12|2020-09-04|Thales Sa|ELECTRONIC DEVICE AND PROCEDURE FOR RECEIVING DATA VIA A REBOUND COMMUNICATION NETWORK, COMMUNICATION SYSTEM AND ASSOCIATED COMPUTER PROGRAM|
    法律状态:
    2015-07-27| PLFP| Fee payment|Year of fee payment: 2 |
    2016-02-19| PLSC| Publication of the preliminary search report|Effective date: 20160219 |
    2016-07-20| PLFP| Fee payment|Year of fee payment: 3 |
    2017-02-17| CD| Change of name or company name|Owner name: SAFRAN ELECTRONICS & DEFENSE, FR Effective date: 20170111 |
    2017-07-20| PLFP| Fee payment|Year of fee payment: 4 |
    2018-07-20| PLFP| Fee payment|Year of fee payment: 5 |
    2019-07-22| PLFP| Fee payment|Year of fee payment: 6 |
    2020-07-21| PLFP| Fee payment|Year of fee payment: 7 |
    2021-07-22| PLFP| Fee payment|Year of fee payment: 8 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1457839A|FR3024932B1|2014-08-14|2014-08-14|METHOD FOR TRANSMITTING DATA WITH IMPROVED ROBUSTNESS AND SET OF DEVICES FOR IMPLEMENTING IT|FR1457839A| FR3024932B1|2014-08-14|2014-08-14|METHOD FOR TRANSMITTING DATA WITH IMPROVED ROBUSTNESS AND SET OF DEVICES FOR IMPLEMENTING IT|
    PCT/EP2015/053239| WO2015124538A1|2014-02-21|2015-02-16|A data transmission method with improved robustness, and a set of devices for performing it|
    US15/120,022| US10477539B2|2014-02-21|2015-02-16|Data transmission method with improved robustness, and a set of devices for performing it|
    CN201580009528.8A| CN106068500B|2014-02-21|2015-02-16|Data transmission method with improved robustness, and for performing one group of equipment of this method|
    [返回顶部]